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AS91L1006BU july 2004 6-port jtag gateway description the as91 l 1 006bu is a one to 6-port jtag gate w ay. it partitions a si ngle jtag ch ain into six se pa rate chai ns. these sep a rate chain s can b e option a lly configu r e d to operate as a singl e chai n. the as91 l 1 006bu devi c e i s u s e d to provide enhanced capabilit ies to the standard ieee1149.1. it enables the ieee1149. 1 interface to be used in a true multi-drop e n viron m ent without any addition al sign als. t h is multi-dro p cap ability enabl es the stand ard iee e 1149.1 inte rface to be use d n o t just for stand alo ne pcb (pri n t ed ci rcuit board ) te sti ng, but al so for compl e te system testing in clud ing all pcbs within a sy stem ba ck plane e n viron m ent. the as91l 1 006bu provi des th e ca pa bility of pa rtitionin g the p c b, into m u ltiple smaller ieee1149.1 scan chain s totally under software control. partitioning the iee e 1149.1 chai ns on th e pcb ha s se veral ben efits whi c h in cl ude ea sie r fault diagn ost i cs capabilitie s a s a fault on on e of the ieee1149.1 local scan ports (ls p s) do es not ren der the pcb untestabl e, faster fla s h prog ram m ing on the p c bs, a nd removal of ieee1149.1 signal loadi ng i s sue s . all of the proto c ol s req u ired for addressin g the as91l1 0 06bu d e vice via the multi-drop capability a n d the protocol s fo r config urin g which of the si x ieee1149.1 lsps o n the as91l10 06bu are to be use d , is handle d via 3 rd party atpg tools fro m vendors li ke asset- intertech an d jtag te chn o logie s . in a multi-drop environ ment it is also possible to perfo rm interconn ect t e sts bet ween multiple p c b s within a system thu s extending th e interconn e c t tests to the back pla n e itself. key features device multi - drop a d d r e s sable via t he ieee 1149.1 p r oto c ol suppo rt for 6 local scan chain s ad dre s sabl e via the ieee 1149.1 interface suppo rt for pass-t hro ugh ? suppo rt for the ieee 114 9.1 userco de inst ru ct ion suppo rt for status inst ructio n ena b ling n o n - intrusive m o n i toring of the system card local sca n p o rt (lsp) ena ble si gnal p r o v ides the ability to use non ieee 1149.1 compliant devices that requi re jtag enabl e signal provides the ability to initiate self-test on a remote p c b via a standard ieee 1149.1 comm and suppo rt for jtag te chnolo g ies a u towr ? feature pinout and feature set compatible (complete se con d so ur ce) wit h t h e firec r o n j t s 06b u device available in a 100-pi n lqf p or a 100-pi n fpbga lead free pa ckag e device block diagram d e vi ce s e le c t io n logi c loc al s c an p o r t p a r k / u n- par k s y nc logi c 114 9 . 1 t a p c o nt r o l l er and b o undar y r e g i s t er s e l e c t i o n log i c p a ss t h r o u g h logi c & loc al sc a n po r t c onnec t i on/ co n f i g lo g i c ls p 1 ls p 2 ls p 3 ls p 4 ls p 5 ls p 6 s t a t u s d a ta us e r c o d e da t a de v i c e ad dr e s s p a s s t h r ough e nabl e p r i m ar y 1 149. 1 j t a g in te r f a c e figure 1 - as91l10 06 bu dev i ce block diagram alliance semiconductor 2575 augusti ne dr i v e ? santa clara, ca 95054 ? t: 40 8-855-4900 ? f: 408-855-49 99 ? w w w . a ls c.com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU AS91L1006BU gateway fu nctional description the b a si c structure of th e as91l1 006 bu device i s sho w n in fig u re-1. the core o f the device is the 16-sta t e ieee1149. 1 tap controlle r state machi ne. all acce sses to the internal registe r s of the as91l10 06bu d e vice are controll ed via this state machin e durin g normal operatio n as pe r the ieee1149.1 stand ard. th e address se lection lo gic enabl es the as91l10 06b u to operate in a multi- dro p environ ment within system ba ckpl ane. the add re ss sele ction logi c com pares t he scann ed ad dre ss to th e slot a ddress valu e pre s ente d o n the i/o of th e as91l1 006 bu devi c e. the lsp park/unp ark logic p r ov ides control throug h in structio ns scanne d in unde r the ieee1149.1 proto c ol, to select, whi c h lsp will be placed into the active, scan chain. the pass- throug h and lsp conne ction logi c select s the sign al path s f o r the lsp i eee1149.1 signal s. the device also suppo rts a pa ss-th r ou gh mode whi c h enabl es the primary ieee1149.1 signals to be routed to any of the lsps. this si gnal routing i s sele ctabl e via i/o pins on the as9 1l10 06bu device. figure-2 sho w s the dev ice sele ction state machi ne. th e as91l1 00 6bu will pe rform an address com pare on th e slot ad dre s s pre s ente d at its i/o a nd the valu e scan ned i n via the ieee1149.1. if the value mat c he s then the as91l10 06b u b e come s selecte d a nd i s ready fo r norm a l acce ss via ieee1149.1 co mma nds. if the address do e s not match then the d e vice will proceed to t he unselect ed mode, where it will remai n until the as91l 1006b u is issued a goto w ait instructio n or a re set occurs via trst or the lsp_reset pin. selec t e d single d e vi ce d e vi ce uns e l e ct ed sel e ct gro u p of devic e s selec t a l l de vi c e s wa it f o r s e lec t io n par k ed- tl r parked -rti park ed- pa useir un pa r k e d park ed- p ause d r figure 2 - as91l10 06 bu selection lo gic state ma chine figure 3 - th e lsp park/unp ark state ma chi n e the lsp park/un park state machi ne co ntrols the in se rtion of the l sps into the curre n t active sca n chai n. the ability to park the lsp in cert ain i eee1149.1 states, enable t he AS91L1006BU to perform several functi ons in clu d ing backpl ane int e rconn ect testing and ic bist. www .a lsc.com alliance semiconductor 2 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU as91l 1006bu detailed mode of operation addre ssing the as91 l10 06bu dev i ce after a test-logi c-re set or po wer-u p , the as91l10 06b u d e vice will be in its wait-f or- s e lect ion st a t e wit h it s t d o pi n tri-st ated, thus avoiding con t ention in a multi-drop e n vironm ent. the as9 1l1 006bu devi c e will re sp ond to a device - sele ct sequ en ce f o r a p a rticul ar ad dre s s that is auto generated by thir d pa rty test tools with respe c t to the add re ss th at is pre - lo a ded on it s s(5..0). once this sequ en ce ha s bee n compl e ted, the as91l10 06bu devi c e will respon d to normal ieee 1149.1 instructions. no te that addresses 60- 63 have be en re se rved and the as91l10 06b u device will not respond if the user sel e cts these addresse s. the as91 l 1 006bu devi c e should be in the wait-fo r -sele c tion mode, whi c h can be entere d int o by i s suing an a s yn ch ro nou s re set (thro ugh th e dea ssertion o f trst) or by issuing a synchro nou s reset (throug h the asse rti on of tms for five cycle s of tck). af ter the device has b een sele cted, it can be i s sued a g o to wait inst ru ct ion. the i n tern al i eee1149.1 st ate ma chin e of the as91l 10 06bu device is ta ken to th e shift-ir pha se and th e requi red device-i d i s shifted into the instru ctio n regi ster . as the ieee1149.1 state machi ne pa sse s throu gh the upd a te-i r pha se, the add re ss i s matched to the value on t he s(5 - 0 ) pins on th e as91l10 06b u d e vice; if t he value s match, then t he as91l1 00 6bu device is sel e cte d and is ready to receive any normal ieee1149.1 comm and. s(5-0 ) value ir (7 ? 0) val ue < 3a hex or 6 0 decim al xxvvvvvv table 1 - as 91l10 06 bu dev i ce selection table www .a lsc.com alliance semiconductor 3 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU table 2 - as 91l10 06 bu multi cas t g r oup selection ta ble table 3 - as 91l10 06 bu dev i ce regis t er des c ription selection mode binary addre ss function single addre s s mode xx00000 0 to xx11101 0 single as91l 1006b u sele cted the tdo of the device wil l be active broad ca st mode xx11101 1 a l l acce ssible as91l10 06b u device s are selecte d for ope ration. tdo on all device s wil l be in highz multi-cast grou p 0 xx11110 0 a c c e s s a l l as91l10 06b u device s that have been pl aced i n grp0 by their mcg r conte n ts multi-cast grou p 1 xx11110 1 a c c e s s a l l as91l10 06b u device s that have been pl aced i n grp1 by their mcg r conte n ts multi-cast grou p 2 xx11111 0 a c c e s s a l l as91l10 06b u device s that have been pl aced i n grp2 by their mcg r conte n ts multi-cast grou p 3 xx11111 1 a c c e s s a l l as91l10 06b u device s that have been pl aced i n grp3 by their mcg r conte n ts regis t er nam e des c ription i n st ru ct ion regi ster as91l10 06b u device addressin g a nd instructio n - decode ieee std. 1149.1 required regi ster bounda ry- scan regi ster ieee std. 1149.1 required regi ster b y pass regi ster ieee std. 1149.1 required regi ster d e vice identification regi ster ieee std. 1149.1 optional regi ster user code regi ster ieee std. 1149.1 optional regi ster status regi ster as91l10 06b u device non intrusive 8 - bit registe r pre load able from the i/o pins self tes t regi ster as91l10 06b u device sp e c ific singl e bit regi ster for initiati ng self testing o n a pcb mode regi ster as91l10 06b u device loca l-po rt config uratio n and control bi ts auto write regi ster as91l10 06b u device auto write featu r e enabl e regi st er lsp as ync re set regi ster as91l10 06b u device async reset regi ster for the lsps www .a lsc.com alliance semiconductor 4 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU table 4 - as 91l10 06 bu dev i ce instruction regis t er op cod e s not e : all ins t ruc t ions ac t on a single selected as 91l10 06 bu dev i ce onl y . * this instru ction cau ses the as9 1 l1 006 bu t o be com e unsele c ted a nd rev e rt to the w a it-fo r- selection s t ate. instructions hex o p - code binary op- code dat a re giste r b y p a s s f f 1 1 1 1 1 1 1 1 b y p a s s regi s t e r e x t e s t 0 0 0000 0 0 0 0 bounda ry-s c a n re giste r s a m p l e / p r e l o a d 8 1 1000 0 0 0 1 bounda ry-s can re giste r idco d e a a 1010 1 0 1 0 device i d e n t i f i c a t i o n regi st e r unpa r k e 7 1110 0 1 1 1 device i d e n t i f i c a t i o n regi st e r p a r k t l r c 5 1100 0 1 0 1 device i d e n t i f i c a t i o n regi st e r p a r k r t i 8 4 1000 0 1 0 0 device i d e n t i f i c a t i o n regi st e r p a r k p a u s e c 6 1 1 0 0 0 1 1 0 device i d e n t i f i c a t i o n regi st e r goto w ait* c 3 1100 0 0 1 1 device i d e n t i f i c a t i o n regi st e r modesele c t 8 e 1 0 0 0 1 1 1 0 m o d e regi s t e r mcg r sele c t 03 0000 0011 multi-cast g r oup regi ster. softreset 8 8 1 0 0 0 1 0 0 0 device i d e n t i f i c a t i o n regi st e r userco d e 9 7 1001 0 1 1 1 user pro g ra mmable 3 2 bit identification regi ster auto wr 98 1001 1000 auto write fe ature ena b le regi ster stest_pcb 99 1001 1001 single bit low pulse, u s ed t o initiate function on pcb (self_test pin) status_by t e 9 a 1001 1 0 1 0 user p r og ram m abl e statu s byte (user_ s tatus_ data pins) lsp_async_reset 9b 10011011 toggles lsp tr st while maintaining the AS91L1006BU in the sele cte d state. other undefi ned tbd tbd device identification regi st er www .a lsc.com alliance semiconductor 5 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU AS91L1006BU device register descriptions by pass register it is a mandatory singl e bit regi ster that can be conn ecte d betwe en pri m _tdi a nd p r im_t do of the as91l1006b u devi c e. multi-cast group regi ster this 2 - bit dat a regi ster e n able s the ho st system to pl ace th e as9 1l10 06bu i n to one of four distin ct a ddre s sabl e group s. mcg r re gis t er bit s [1..0] binar y selec t ion addr ess mc gr gr ou p 0 0 x x 1 1 1 1 0 0 g r p 0 0 1 x x 1 1 1 1 0 1 g r p 1 1 0 x x 1 1 1 1 1 0 g r p 2 1 1 x x 1 1 1 1 1 1 g r p 3 table 5 - mul t icas t group register ma pping note: th e mcg r is rese t to 00 upon r eceiv i ng trst or the entering of th e test-logic - reset sta t e . idcode re gister it is an optional 32-bit reg i ster that ca n be con n e c ted be tween prim _ t di and pri m _tdo of the as91l1 0 06bu d e vice . the co nte n ts of the idco de regi ster will b e l oade d with the follo wing data whe n t he as91 l10 06bu ente r s te st-lo g ic- re set or pa sse s throu gh captu r e - ir: "00000 000 00 0000 0010 000 0110 1101 111 " bits 0 to 11 indic a te alsc j e dec id value of: ?001 101 101 1 11? bits 12 to 27 indicate the part num b e r of the device: ?0 000 0000 0001 000 0? bits 28 to 31 indi cate th e revisio n of th e devi c e: ?000 0? usercode register the usercode i s a n 8 - bit regi ster th at ca n be a ddressed via stand ard ieee1149.1 comm and s, whi c h a r e aut omatically ge nerate d by third pa rty test tools. as 91l1 006b u returns all z e ro es if r ead fr o m th is re g i s t er u s eru ser an d does have the ability to writ e into this register. * the as91 l 1006 bu is a complete s e c ond sour ce and pin for pin replace ment of the firecron jts 06bu dev i ce. www .a lsc.com alliance semiconductor 6 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU self_test register the as91 l 1006b u d e vice sup p o r ts a singl e outp u t pin that ca n be co ntroll ed via th e ieee1149.1 interface. w hen the i n struction is loade d into the as91l1 0 06bu in stru ct ion regi ste r , a sin g le bit data regi ster is con n e c te d whi c h is alway s re set to logic zero whe n the tap state machi ne ent ers ca pture - dr. thi s will cau s e the self_test pin to pulse low for o ne cy cle of tck, durin g the up date-dr pha se. thi s low going p u lse can be used t o initiate self-tests on p c b?s in a rack via the jtag interface. lsp_asy n c_rst reg i ster the as91l 1 006bu device su ppo rts a s ync reset tests o n the devices conn ecte d to the lsps. the stan dard metho d of p e rformi ng the s e te st s by utilizing the p r imary t r st pin ca nnot be used a s it will cause the AS91L1006BU to deselect and it s internal re gisters to be re set. in orde r to enabl e asyn c reset tests on lsp s , the te st to ol should instru ct the d e vice to togg le the lsp reset pin s while m a intai n ing the set up informati on in the as91l10 06b u. wh en th e instructio n is loa ded into the as 91l1 006b u instru ction registe r , a singl e bit dat a regi ster i s con n e c ted as the data regi ster which is alway s reset to logic zero wh en the tap state machi ne e n ters captu r e-dr. this will cause the lsp trst pi ns to pul se l o w for one tck cycl e, during the upd a te-dr ph ase. autow r register this i s a 6-bit regi ster that controls the p a ss- throug h of the jtag t e ch nolo g ies autowr ? sign al to an y lsp. the regi ster i s re set to all zeros whe n e n tering the t e st-l ogi c-re set state. note: th e mcg r is rese t to 00 upon r eceiv i ng trst or the entering of th e test-logic - reset s t a t e aut o wr regis t er (bit 2 ? bit 0) lsp 3 aut o wr signal lsp 2 aut o wr signal lsp 1 aut o wr signal 000 high z high z high z 001 high z high z active 0 1 1 h i g h z a c t i v e a c t i v e 100 active high z high z 1 0 1 a c t i v e h i g h z a c t i v e 1 1 0 a c t i v e a c t i v e h i g h z 1 1 1 a c t i v e a c t i v e a c t i v e aut o wr regis t er (bit 5 ? bit 3) lsp 6 aut o wr signal lsp 5 aut o wr signal lsp 4 aut o wr signal 000 high z high z high z 001 high z high z active 0 1 1 h i g h z a c t i v e a c t i v e 100 active high z high z 1 0 1 a c t i v e h i g h z a c t i v e 1 1 0 a c t i v e a c t i v e h i g h z 1 1 1 a c t i v e a c t i v e a c t i v e table 6 - autowr regis t er map p ing www .a lsc.com alliance semiconductor 7 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU mode_sel ect register the mod e_s elect regi ster allows the l s p of the as91 l100 6bu to be conn ecte d in vario u s different con f iguration s . a lsp is selecte d for con n e c tion wi thin the sca n chai n by the conte n ts of the mode_s e l ect regi ste r . if the lsp is not parked in a stable stat e, i.e.: pause-dr, pau s e-i r , run - te st-idl e or te st- logi c-re set, it will be co n necte d into the active scan chain. if all lsps are p a rked i n a stabl e state, then the as91l1 006bu will perfo rm a bypass of the 6-lsp ch ai n se ction. in this way if both sectio ns are i n t he bypass m o d e then th e as91l10 06b u i s perfo rmi ng a loo pba ck of tdi - >regi ster->t d o to the ho st device. mode_sele c t regis t er (bit 15 -> bit 8) lsp configu r ation (if por t unpar ked ) x x x 0 x 0 0 0 t d i ->regist er->lsp_dat a x x x 0 x 0 0 1 t d i ->regist er->lsp1->p a d - > lsp_data x x x 0 x 0 1 0 t d i ->regist er->lsp2->p a d - > lsp_data x x x 0 x 0 1 1 t d i ->regist er->lsp1->p a d- > l sp2-> pad-> lsp_data x x x 0 x 1 0 0 t d i ->regist er->lsp3->p a d - > lsp_data x x x 0 x 1 0 1 t d i ->regist er->lsp1->p a d- > l sp3-> pad-> lsp_data x x x 0 x 1 1 0 t d i ->regist er->lsp2->p a d- > l sp3-> pad-> lsp_data x x x 0 x 1 1 1 t d i ->regist er->lsp1->p a d- > l sp2-> pad-> lsp3-> pad-> lsp_data mode_sele c t register (bit 7 -> bit 0) lsp configu r ation (if por t unpar ked ) x x x 0 x 0 0 0 l s p _ d a t a - > t d o x x x 0 x 0 0 1 l s p _ d a t a ->lsp4->pa d- >t do x x x 0 x 0 1 0 l s p _ d a t a ->lsp5->pa d- >t do x x x 0 x 0 1 1 l s p _ d a t a ->lsp4->pa d- > l sp5-> pad-> tdo x x x 0 x 1 0 0 l s p _ d a t a ->lsp6->pa d- >t do x x x 0 x 1 0 1 l s p _ d a t a ->lsp4->pa d- > l sp6-> pad-> tdo x x x 0 x 1 1 0 l s p _ d a t a ->lsp5->pa d- > l sp6-> pad-> tdo x x x 0 x 1 1 1 l s p _ d a t a ->lsp4->pa d- > l sp5-> pad-> lsp6-> pad- >t do table 7 - mo de select re gister ma pping x = don?t care regis t er = a s 91l10 06b u device in stru ction re giste r or any of the as91l10 06b u device test data regi ste r s. pad = in se rtion of a 1-bit regist e r for dat a synchro n ization. upo n enteri n g test-logi c-re set, the re gist er bit s will be loade d wi th ?0000 000 ?. www .a lsc.com alliance semiconductor 8 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU pass through support within the AS91L1006BU device the as91 l 1006b u d e vice sup p o r ts a pass-t hro u g h mod e whe r e the prim ary or ma ster ieee1149.1 jtag si gnal s ca n be ro uted to any one of the l sps. when t h is mod e is a c tivated, the ?de bug e nab le? si gnal fo r that lsp will go a c tive, w h ic h c a n be us e d to p l a c e a pr oc ess o r su ch as the mpc82 60 into b d m (ba c kgro und deb ug mode ), if required. if no pr ocesso rs are pre s ent in the lsp, the pass-t hro u g h mode can be used to assist in the gene ration of the test vectors o r memory te sts for the devi c es th at are li nke d into the sele cted lsp. the pass-throug h feature ha s the effect of simplifying th e test ve cto r gene ration for the lsp, as it also h a s the effe ct of rem o ving the as91l 10 06bu device from th e te st vecto r gene ration p r oce s s. pa ss_thru_enable pa ss_thru_sel( 2 ) pa ss_thru_sel( 1 ) pa ss_thru_sel( 0 ) activ e lsp high x x x normal operation l o w l o w l o w l o w l s p 1 l o w l o w l o w h i g h l s p 2 l o w l o w h i g h l o w l s p 3 l o w l o w h i g h h i g h l s p 4 l o w h i g h l o w l o w l s p 5 l o w h i g h l o w h i g h l s p 6 table 8 - pas s throug h mode in as91 l1006 bu note: when pass_thru_enable is deasserte d (logic ?1?), then the lsps are under control of the as91l 1006bu dev i ce l ogic. when pass_ thru_enable is asserted (logic ?0 ?) an d if an in v a lid co mbination is presen te d o n the pass_ thru_sel lines, then all lsps are tri-sta t ed . www .a lsc.com alliance semiconductor 9 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU signal descriptio n pin name pin type pin num be r lqfp pin num be r fpbg a description stable state after por t/re set lsp1_tck out 31 h4 ieee1149.1 test cl ock on lsp 1 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 000. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t c k lsp1_tms out 32 j4 ieee1149.1 test mod e select on lsp 1 when pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 000. this pin i s tri-stated for all other combi nation s . logi c '1' lsp1_tdo out 35 h5 ieee1149.1 test data ou t on lsp 1 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 000. this pin i s tri-stated for all other combi nation s . logi c '1' lsp1_tdi in 33 k4 ieee1149.1 test data in on lsp 1 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 000. lsp1_trst out 29 k3 ieee1149.1 test reset on lsp 1 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 000. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t r st www .a lsc.com alliance semiconductor 10 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU pin name pin type pin num be r lqfp pin num be r fpbg a description stable state after por t/re set lsp1_autow r out 30 j3 flash, me mor y auto-write on lsp 1 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 000; prim_auto w r is ro uted to output. this pin i s tri-stated for all other combi nation s . logi c '1' lsp1_de out 28 j2 pass-t hro u g h deb ug ena b le output on lo cal sca n port 1. active low ou tput when pass_thru_enable = 0 and pass_thru_sel[2:0] = 000. this pin i s hig h for all other combi nation s . logi c '1' lsp2_tck out 41 j6 ieee1149.1 test cl ock on lsp 2 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 001. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t c k lsp2_tms out 42 h6 ieee1149.1 test mod e select on lsp 2 when pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 001. this pin i s tri-stated for all other combi nation s . logi c '1' lsp2_tdo out 45 j7 ieee1149.1 test data ou t on lsp 2 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 001. this pin i s tri-stated for all other combi nation s . logi c '1' www .a lsc.com alliance semiconductor 11 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU pin name pin type pin num be r lqfp pin num be r fpbg a description stable state after por t/re set lsp2_tdi in 44 k7 ieee1149.1 test data in on lsp 2 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 001. lsp2_trst out 37 k5 ieee1149.1 test reset on lsp 2 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 001. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t r st lsp2_autow r out 40 k6 flash, me mor y auto-write on lsp 2 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 001; prim_auto w r is ro uted to output. this pin i s tri-stated for all other combi nation s . logi c '1' lsp2_de out 36 j5 pass_thru debug enabl e output on lsp 2. active low ou tput when pass_thru_enable = 0 and pass_thru_sel[2:0] = 001. this pin i s hig h for all other combi nation s . logi c '1' lsp3_tck out 49 k9 ieee1149.1 test cl ock on lsp 3 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 010. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t c k www .a lsc.com alliance semiconductor 12 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU pin name pin type pin num be r lqfp pin num be r fpbg a description stable state after por t/re set lsp3_tms out 50 k10 ieee1149.1 test mod e select on lsp 3 when pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 010. this pin i s tri-stated for all other combi nation s . logi c '1' lsp3_tdo out 53 h10 ieee1149.1 test data ou t on lsp 3 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 010. this pin i s tri-stated for all other combi nation s . logi c '1' lsp3_tdi in 52 j10 ieee1149.1 test data in on lsp 3 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 010. lsp3_trst out 47 j8 ieee1149.1 test reset on lsp 3 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 010. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t r st lsp3_lsp_ autowr out 48 k8 flash, me mor y auto-write on lsp 3 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 010; prim_auto w r is ro uted to output. this pin i s tri-stated for all other combi nation s . logi c '1' www .a lsc.com alliance semiconductor 13 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
www.alsc.com alliance semiconductor 14 july 2004 AS91L1006BU 2003, 2004 ? copyright alliance semiconductor corporation. all rights reserved. pin name pin type pin number lqfp pin number fpbga description stable state after port/reset lsp3_de out 46 h7 pass_thru debug enable output on lsp 3. active low output when pass_thru_enable = 0 and pass_thru_sel[2:0] = 010. this pin is high for all other combinations. logic '1' lsp4_tck out 79 a8 ieee1149.1 test clock on lsp 4 when pass_thru_enable is high. pin is in pass-through mode when pass_thru_enable = 0 and pass_thru_sel[2:0] = 011. this pin is tri-stated for all other combinations. buffered version of signal present on primary tck lsp4_tms out 78 a9 ieee1149.1 test mode select on lsp 4 when pass_thru_enable is high. pin is in pass-through mode when pass_thru_enable = 0 and pass_thru_sel[2:0] = 011. this pin is tri-stated for all other combinations. logic '1' lsp4_tdo out 76 b10 ieee1149.1 test data out on lsp 4 when pass_thru_enable is high. pin is in pass-through mode when pass_thru_enable = 0 and pass_thru_sel[2:0] = 011. this pin is tri-stated for all other combinations. logic '1' lsp4_tdi in 77 b9 ieee1149.1 test data in on lsp 4 when pass_thru_enable is high. pin is in pass-through mode when pass_thru_enable = 0 and pass_thru_sel[2:0] = 011. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU pin name pin type pin num be r lqfp pin num be r fpbg a description stable state after por t/re set lsp4_trst out 81 a7 ieee1149.1 test reset on lsp 4 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 011. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t r st lsp4_autow r out 80 b8 flash, me mor y auto-write on lsp 4 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 011; prim_auto w r is ro uted to output. this pin i s tri-stated for all other combi nation s . logi c '1' lsp4_de out 83 b7 pass_thru debug enabl e output on lsp 4. active low ou tput when pass_thru_enable = 0 and pass_thru_sel[2:0] = 011. this pin i s hig h for all other combi nation s . logi c '1' lsp5_tck out 70 d10 ieee1149.1 test cl ock on lsp 5 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 100. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t c k lsp5_tms out 69 d9 ieee1149.1 test mod e select on lsp 5 when pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 100. this pin i s tri-stated for all other combi nation s . logi c '1' www .a lsc.com alliance semiconductor 15 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU pin name pin type pin num be r lqfp pin num be r fpbg a description stable state after por t/re set lsp5_tdo out 67 e8 ieee1149.1 test data ou t on lsp 5 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 100. this pin i s tri-stated for all other combi nation s . logi c '1' lsp5_tdi in 68 e7 ieee1149.1 test data in on lsp 5 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 100. lsp5_trst out 72 c9 ieee1149.1 test reset on lsp 5 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 100. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t r st lsp5_autow r out 71 d8 flash, me mor y auto-write on lsp 5 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 100; prim_auto w r is ro uted to output. this pin i s tri-stated for all other combi nation s . logi c '1' lsp5_de 75 c10 pass_thru debug enabl e output on lsp 5. active low ou tput when pass_thru_enable = 0 and pass_thru_sel[2:0] = 100. this pin i s hig h for all other combi nation s . logi c '1' www .a lsc.com alliance semiconductor 16 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU pin name pin type pin num be r lqfp pin num be r fpbg a description stable state after por t/re set lsp6_tck out 61 f10 ieee1149.1 test cl ock on lsp 6 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 101. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t c k lsp6_tms out 60 f9 ieee1149.1 test mod e select on lsp 6 when pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 101. this pin i s tri-stated for all other combi nation s . logi c '1' lsp6_tdo out 57 g10 ieee1149.1 test data ou t on lsp 6 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 101. this pin i s tri-stated for all other combi nation s . logi c '1' lsp6_tdi in 58 g8 ieee1149.1 test data in on lsp 6 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 101. lsp6_trst out 64 e9 ieee1149.1 test reset on lsp 5 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 101. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t r st www .a lsc.com alliance semiconductor 17 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU pin name pin type pin num be r lqfp pin num be r fpbg a description stable state after por t/re set lsp6_autow r out 63 f7 flash, me mor y auto-write on lsp 6 when pass_thru_e nab l e is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[2:0] = 101; prim_auto w r is ro uted to output. this pin i s tri-stated for all other combi nation s . logi c '1' lsp6_de out 65 e10 pass_thru debug enabl e output on lsp 6. active low ou tput when pass_thru_enable = 0 and pass_thru_sel[2:0] = 101. this pin i s hig h for all other combi nation s . logi c '1' prim_t c k i n 8 7 a 6 ieee1149.1 primary te st clo ck input. prim_tms in 21 g2 ieee1149.1 primary te st mode selec t input. prim_t do out 20 g1 ieee1149.1 primary te st data output. this pin is tri-state d whe n as91l10 06b uis n o t sele ct ed. highz prim_t di in 19 g3 ieee1149.1 primary te st data input prim_t rst in 22 h2 ieee1149.1 primary te st re set input. this ac tive low as ync h ronous reset input sig nal pl ace s as91l 1 006 u in wait-fo r-sel e c tion state. prim_auto w r in 16 f1 primary auto-write inp u t controlle d by test equip m ent to sho r ten flash memory programming. s [ 5 : 0 ] i n 8,7,6,5,100, 99 d2,d 1,d3, c 2,b2,a2 as91l10 06b u slot addre ss[5:0] inputs. used to set a ddre s s at whi c h as91l10 06b u will re sp on d; typically set by hard w i r ed conn ectio n on the backpl ane. *toe in 88 b6 test outp ut enable input. tri-state s all lsps, whe n asserte d low. www .a lsc.com alliance semiconductor 18 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU pin name pin type pin num be r lqfp pin num be r fpbg a description stable state after por t/re set lsp_reset _n in 14 f4 lsp reset input. active low re sets as91 l 1 006bu to ?wait-for-sel e ction ? state and pul se s all lsp trst output pins t o low. this resets all devic es with trst function; typically this sign a l would b e con n e c ted to a power-on - reset function. as91l10 06b u_ selected o u t 2 5 k 1 as91l10 06b u_sele cted o u t p u t . active low wh en as91l1 00 6bu is sele cted; typically used to control off board bufferi ng. logi c '1' lsp_enabl e o u t 2 4 j 1 lsp enabled o u t p u t . active low wh en as91l1 00 6bu is sele cted; typically used to set ieee1149.1 complian c e e n able pin s on devices. logi c '1' user_status _ byte[7:0] in 84, 85, 92, 93, 94, 96, 97, 98 (msb-lsb) c7,c 6,c5, c 4,b4,a4,b3, a3(msb- lsb) as91l10 06b u status_byte inputs. used to provi de statu s info rmation of the pcb und er test ba ck to the test maste r via the ieee1149.1 bus. eight sign als level s can be mo nitored a nd then rep o rte d via the ieee1149.1 b u s in a non intru s ive mann er. self_test out 27 k2 provide s a lo w goin g outp u t pulse unde r co mma nd from the ieee1149.1 bus, which ca n be used to s t art s e lf-tes t func tions on a pcb. logi c '1' pass_thru_ enable in 9 e4 pass_thru enable input . active high di sabl es pa ss-thro ugh mode. active low en able s pass-t hrou gh mode. pass_thru_ sel12:0] i n 1 3 , 1 2 , 1 0 (msb-lsb) e2,e1,e3 (msb-lsb) pass_thru select inputs. used to sel e ct active routin g of pass- thro ugh p o rt s ena bled by active low on pass_thru_enable pin. 000 = lsp1 001 = lsp2 010 = lsp3 011 = lsp4 100 = lsp5 101 = lsp6 www .a lsc.com alliance semiconductor 19 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU pin name pin type pin num be r lqfp pin num be r fpbg a description stable state after por t/re set gnd power 38, 86, 11, 26, 43, 59, 74, 95, 2, 17, 54, 55 90 d6, g5, c3, d7, e5, f6, g4,h8, h9, j 9 ,b1, a5, f2 grou nd pin s . vcc power 39, 91, 3, 18, 34, 51, 66, 82,23,56 d5, g6, c8, d4, e6, f5, g7, h3,g9, h1 vcc pin s . asic_test_ en in 89 b5 facto r y test_ e nable input. this pin sho u l d be left unconne cted. asic_tck in 62 f8 ieee1149.1 asic test cl ock input. asic_tms in 15 f3 ieee1149.1 asic test mode sele ct. input a s i c _ t d o o u t 7 3 a 1 0 ieee1149.1 asic test cl ock output. asic_tdi in 4 a1 ieee1149.1 asic test cl ock input. no conn ect s 1 c1 table 9 - as 91l00 06 bu signal descr iption absolute maximum ratings parameter maximum range supply voltage (vcc) -0.3v to 5.5v dc inp u t voltage (vi) -0.5v to vcc +0.5v max sink cu rrent whe n vi = -0.5v -20ma max sou r ce current wh en vi = vcc + 0. 5v +20ma max jun c tion tempe r ature with power a pplied tj +12 5 deg ree s c max storage temperature -55 to +150 d egre e c table 10 - absolute m axi mum rating s note: str ess abov e the stated maximu m v a lues ma y cause irreparable dam a ge to the d e v i ce. corre ct op er ation of the dev i ce at these v a lues is not guar a nte e d. recommended operating conditions www .a lsc.com alliance semiconductor 20 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU parameter opera t ing range supply voltage (vcc) 3.0v to 3.6v input voltage (vi) 0v to vcc output voltag e (vo) 0v to vcc operating te mperature (t a) comm ercial 0 c to 70 c industri a l (ta ) -40 de g c to +85 d eg c, 3. 00v to 3.6v table 11 - recommende d opera t ing conditio n s www .a lsc.com alliance semiconductor 21 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU ac electrical characteristics lsp s i g n a l tpd tco toe th tc l tc w tch tc k td o td i tm s hi g h z hi g h z tsu figure 4 - as91l10 06 bu ac timing diagram symbol parameter min max units tcw tck clo c k pu lse wi dth 100 - ns tch tck pul se wi dth high 50 - ns tcl tck pul se wi dth low 50 - ns tsu tck setup time 30 - ns th tck hol d time 40 - ns toe neg edg e tck to valid data enabl e 20 - ns tco neg edg e tck to valid data 15 - ns tpd pass th rou g h mode prima r y/lsp del a y - 10 ns table 12 - as91l10 06 bu ac timing informa t ion www .a lsc.com alliance semiconductor 22 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU dc electrical characteristics sy mbol parameter max min conditio n vih minimum hi g h input voltage 5.25 2.0 vil maximum lo w input voltage 0.8v -0.3v sy mbol parameter value conditio n voh minimum hi gh output voltage 2.4v ioh=2 4 ma or 8ma as defin ed by pin vol minimum lowoutput voltage 0.4v iol=24ma o r 8ma as defin ed by pin ioz tris tate output leak age -10 o r 10 ma ic c maximum qui ece nnt s u pp ly c u rr ent 2ma i ccd maximum dynamic s u pp ly c u rr ent 80ma tck freq e q u a l to 10 mhz table 13 - as91l10 06 bu dc electric a l chara c te ristics packaging information the as91l1 0 06bu is avail able in a 10 0-pin lqfp o r a 100-pin fp bga lead fre e packa ge. d1 sq u a r e 1 d s qua r e 3 d 1 ba si c 14 . 0 0 d ba si c 18 . 0 0 l 0. 15 0. 6 0 a 2 m i n no m m a x 1 . 35 1 . 40 1. 4 5 l1 re f 1. 0 0 a ma x . 1. 6 0 b mi n m a x 0 . 1 7 0 . 2 7 a 1 0. 0 5 0 . 15 e ba si c 0. 5 0 j e d e c re f # ms - 0 2 6 cc c ma x 0. 0 8 dd d no m 0. 0 8 sym b o l 100 le a d to l . le a d s mi n m a x not e s : 1 . a l l l i n e a r d i m e n s io n s a r e i n m i l l i m e t e r s . 2 . pl as t i c bo dy d i m e n s i o ns do n o t i n c l u d e f l as h o r pr o t usi o n . m ax al l o w a bl e 0 . 2 5 per si de. 3 . l ead c o un t o n d r a w i n g n o t re presentat i ve o f a c tual packag e. 3. m a 0.2 5 0 . 09/0.20 t y p 0 - 7 typ l l1 b a1 - c - cc c l e ad co pl a n a r i t y al a l al a- b s d s a2 a 12 n o m 12 n o m e figure 5 - l q fp-1 00 www .a lsc.com alliance semiconductor 21 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU r e visions r e v . d e s c r i p t i o n e c n d a t e a initial document release. 91253 12-04- 01 b updated ball cop l anarit y limits from 0.20mm to 0.15 mm. d e a b 2 c 0.15 c d1 e1 c d g h i k 1 2 3 4 5 6 7 8 9 1 0 f e b a b 0 . 2 5 m c 0 . 2 5 m c a b dimensions s y mb o l m i n . no m . m a x . a - - - - 1 . 7 0 a 1 0 . 3 0 - - - - a 2 0 . 2 5 - - 1 . 1 0 b 0 . 5 0 0 . 6 0 0 . 7 0 d 1 1 . 0 0 b s c d 1 9 . 0 0 b s c e 1 1 . 0 0 b s c e 1 9 . 0 0 b s c e 1 . 0 0 packag e num ber fbg a 010 0-11 f j e dec ref # mo-19 2 var. a a c-1 figure 6 - fp bg a-1 00 www .a lsc.com alliance semiconductor 22 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU device selector g u ide and ordering information as91l x xxx u u - cc pp - temp - l al i a n c e s emi c ond uc t o r syste m so lu tio n d e vice fa mily 1001 1002 1003 1006 pro duc t v e rs i o n s = s t andar d u = 16 - b it use r cod e bu = 8- bi t s t at us / u s e r c ode e = e nhanc ed c = com mer c i al (0 t o 70 d egrees c) i = i ndus t r i a l (- 40 t o 85 deg rees c) pa cka ge l 100 = 10 0 pi n lqf p f 100 = 1 00 pi n f p bga c l o ck spe e d 10 = 10 m h z tck 40 = 40 m h z tck b l ank = le aded f = l ead f r ee g = green figure 7 - pa rt numb erin g guide www .a lsc.com alliance semiconductor 23 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU part number des c ription as91l10 06b u ? 10l 100 -c jtag 6 - port gateway, 100-pin l q fp packa ge, co mmercial as91l10 06b u ? 10l 100 -cf jtag 6 - port gateway, 100-pin l q fp packa ge, co mmercial, lea d free as91l10 06b u ? 10l 100 -i jtag 6 - port gateway, 100-pin l q fp packa ge, ind u strial as91l10 06b u ? 10l 100 -if jtag 6 - port gateway, 100-pin l q fp packa ge, ind u strial, lea d free as91l10 06b u ? 10f1 0 0 - c j t ag 6-port gateway 100-pin fpbga packa ge, co mmercial as91l10 06b u ? 10f1 0 0 - cg jtag 6 - port gateway 100 -pin fpbga, comm ercial, gree n pa ckag e as91l10 06b u ? 10f1 0 0 - i j t ag 6-port gateway 100-pin fpbga packa ge, ind u strial as91l10 06b u ? 10f1 0 0 - ig jtag 6 - port gateway 100 -pin fpbga, indu strial, gre en pa ckage as91l10 06b u ? 40l 100 -cf jtag 6 - port gateway, 100-pin l q fp packa ge, co mmercial, lea d free, 40 mhz tck as91l10 06b u ? 40l 100 -if jtag 6 - port gateway, 100-pin l q fp packa ge, ind u strial, lea d free, 40 mhz tck as91l10 06b u ? 40f1 0 0 - cg jtag 6 - port gateway 100 -pin fpbga, comm ercial, gree n pa ckag e, 40 mhz tck as91l10 06b u ? 40f1 0 0 - ig jtag 6 - port gateway 100 -pin fpbga, indu strial, gre en pa ckage, 40 mhz tck table 14 - valid part number combinations www .a lsc.com alliance semiconductor 24 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU packag e options dev i ce master des c ription fpbg a-1 00 (1mm pitch) lqfp -100 as91l10 01 jtag te st controlle r x x as91l10 02 jtag te st seque ncer x x as91l10 03 u 3 - p o r t g a t e w a y x x as91l10 06b u 6 - p o r t g a t e w a y x x table 15 - jt ag contr o ller produc t family www .a lsc.com alliance semiconductor 25 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com .com 4 .com u datasheet
july 2004 AS91L1006BU www .a lsc.com alliance semiconductor 26 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed. .com .com .com .com 4 .com u datasheet

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